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DSD
2009
IEEE
124views Hardware» more  DSD 2009»
14 years 3 months ago
Network-on-Chip Architecture Exploration Framework
— In this paper, we present a novel framework for the automated generation of Network-on-Chips (NoC) architectures, that enables architecture exploration and optimization. The au...
Timo Schönwald, Jochen Zimmermann, Oliver Bri...
VLSID
2006
IEEE
94views VLSI» more  VLSID 2006»
14 years 2 months ago
On the Size and Generation of Minimal N-Detection Tests
The main result of this paper, proved as a theorem, is that a lower bound on the number of test vectors that detect each fault at least N times is N
Kalyana R. Kantipudi
CORR
2010
Springer
59views Education» more  CORR 2010»
13 years 8 months ago
Hybrid approach for Image Encryption Using SCAN Patterns and Carrier Images
We propose a hybrid technique for image encryption which employs the concept of carrier image and SCAN patterns generated by SCAN methodology. Although it involves existing method ...
Panduranga H. T, Naveen Kumar S. K
DATE
2003
IEEE
94views Hardware» more  DATE 2003»
14 years 1 months ago
Platform-Based Testbench Generation
This paper presents a new technology that accelerates system verification. In a real life example, we achieved a speed-up of a factor of about 5000. The key for this speed-up is a...
Renate Henftling, Andreas Zinn, Matthias Bauer, Wo...