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HPCA
2005
IEEE
14 years 9 months ago
Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain Processors
Dynamic voltage and frequency scaling (DVFS) is a widely-used method for energy-efficient computing. In this paper, we present a new intra-task online DVFS scheme for multiple clo...
Qiang Wu, Philo Juang, Margaret Martonosi, Douglas...
DAC
1996
ACM
14 years 1 months ago
Optimal Clock Skew Scheduling Tolerant to Process Variations
1- A methodology is presented in this paper for determining an optimal set of clock path delays for designing high performance VLSI/ULSI-based clock distribution networks. This met...
José Luis Neves, Eby G. Friedman
DSN
2007
IEEE
14 years 3 months ago
Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...
Christopher LaFrieda, Engin Ipek, José F. M...
DSN
2005
IEEE
14 years 2 months ago
ReStore: Symptom Based Soft Error Detection in Microprocessors
Device scaling and large scale integration have led to growing concerns about soft errors in microprocessors. To date, in all but the most demanding applications, implementing par...
Nicholas J. Wang, Sanjay J. Patel
MOBICOM
2010
ACM
13 years 9 months ago
CTRL: a self-organizing femtocell management architecture for co-channel deployment
Femtocell technology has been drawing considerable attention as a cost-effective means of improving cellular coverage and capacity. However, under co-channel deployment, femtocell...
Ji-Hoon Yun, Kang G. Shin