472 search results - page 51 / 95 » Performance Evaluation of Memory Caches in Multiprocessors |
ICS
2004
Tsinghua U.
14 years 2 months ago
2004
Tsinghua U.
Cache hierarchies have been traditionally designed for usage by a single application, thread or core. As multi-threaded (MT) and multi-core (CMP) platform architectures emerge and...
ICS
2009
Tsinghua U.
14 years 3 months ago
2009
Tsinghua U.
The L2 cache is commonly managed using LRU policy. For workloads that have a working set larger than L2 cache, LRU behaves poorly, resulting in a great number of less reused lines...
HPCA
2009
IEEE
14 years 9 months ago
2009
IEEE
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
ISCA
2006
IEEE
14 years 2 months ago
2006
IEEE
Improvements in semiconductor technology have made it possible to include multiple processor cores on a single die. Chip Multi-Processors (CMP) are an attractive choice for future...
CODES
2007
IEEE
14 years 3 months ago
2007
IEEE
Heterogeneous multiprocessors are emerging as the dominant implementation approach to embedded multiprocessor systems. In addition to having processing elements suited to the targ...