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» Performance Evaluation of Memory Caches in Multiprocessors
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HPCA
2000
IEEE
14 years 1 months ago
Impact of Chip-Level Integration on Performance of OLTP Workloads
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...
Luiz André Barroso, Kourosh Gharachorloo, A...
MICRO
1995
IEEE
108views Hardware» more  MICRO 1995»
14 years 11 days ago
SPAID: software prefetching in pointer- and call-intensive environments
Software prefetching, typically in the context of numericor loop-intensive benchmarks, has been proposed as one remedy for the performance bottleneck imposed on computer systems b...
Mikko H. Lipasti, William J. Schmidt, Steven R. Ku...
ICCD
2005
IEEE
110views Hardware» more  ICCD 2005»
14 years 5 months ago
Near-memory Caching for Improved Energy Consumption
Main memory has become one of the largest contributors to overall energy consumption and offers many opportunities for power/energy reduction. In this paper, we propose a PowerAw...
Nevine AbouGhazaleh, Bruce R. Childers, Daniel Mos...
SC
1995
ACM
14 years 10 days ago
Predicting Application Behavior in Large Scale Shared-memory Multiprocessors
In this paper we present an analytical-based framework for parallel program performance prediction. The main thrust of this work is to provide a means for treating realistic appli...
Karim Harzallah, Kenneth C. Sevcik
ISLPED
2003
ACM
87views Hardware» more  ISLPED 2003»
14 years 2 months ago
On load latency in low-power caches
Many of the recently proposed techniques to reduce power consumption in caches introduce an additional level of nondeterminism in cache access latency. Due to this additional late...
Soontae Kim, Narayanan Vijaykrishnan, Mary Jane Ir...