Sciweavers

472 search results - page 92 / 95
» Performance Evaluation of Memory Caches in Multiprocessors
Sort
View
PPPJ
2009
ACM
14 years 4 days ago
Virtual reuse distance analysis of SPECjvm2008 data locality
Reuse distance analysis has been proved promising in evaluating and predicting data locality for programs written in Fortran or C/C++. But its effect has not been examined for ap...
Xiaoming Gu, Xiao-Feng Li, Buqi Cheng, Eric Huang
ASPLOS
2010
ACM
14 years 2 months ago
Addressing shared resource contention in multicore processors via scheduling
Contention for shared resources on multicore processors remains an unsolved problem in existing systems despite significant research efforts dedicated to this problem in the past...
Sergey Zhuravlev, Sergey Blagodurov, Alexandra Fed...
ACMSE
2004
ACM
14 years 27 days ago
Execution characteristics of SPEC CPU2000 benchmarks: Intel C++ vs. Microsoft VC++
Modern processors include features such as deep pipelining, multilevel cache hierarchy, branch predictors, out of order execution engine, and advanced floating point and multimedi...
Swathi Tanjore Gurumani, Aleksandar Milenkovic
ISCA
2011
IEEE
258views Hardware» more  ISCA 2011»
12 years 11 months ago
A case for heterogeneous on-chip interconnects for CMPs
Network-on-chip (NoC) has become a critical shared resource in the emerging Chip Multiprocessor (CMP) era. Most prior NoC designs have used the same type of router across the enti...
Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. ...
IEEEPACT
2007
IEEE
14 years 1 months ago
A Flexible Heterogeneous Multi-Core Architecture
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...
Miquel Pericàs, Adrián Cristal, Fran...