Task-selection policies are critical to the performance of any architecture that uses speculation to extract parallel tasks from a sequential thread. This paper demonstrates that ...
Mayank Agarwal, Kshitiz Malik, Kevin M. Woley, Sam...
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
Shiliang Hu, Ilhyun Kim, Mikko H. Lipasti, James E...
Tiny, low-cost sensor devices are expected to be failure-prone and hence in many realistic deployment scenarios for sensor networks these nodes are deployed in higher than necessa...
Community wireless networks (CWNs) have been proposed to spread broadband network access to underprivileged, underprovisioned and remote areas. Research has focused on optimizing ...
Saumitra M. Das, Konstantina Papagiannaki, Suman B...
Clustered ILP processors are characterized by a large number of non-centralized on-chip resources grouped into clusters. Traditional code generation schemes for these processors c...
Krishnan Kailas, Kemal Ebcioglu, Ashok K. Agrawala