Sciweavers

572 search results - page 44 / 115
» Performance Evaluation of a C Library Based Multithreaded ...
Sort
View
ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
14 years 2 months ago
Multiple Instruction Stream Processor
Microprocessor design is undergoing a major paradigm shift towards multi-core designs, in anticipation that future performance gains will come from exploiting threadlevel parallel...
Richard A. Hankins, Gautham N. Chinya, Jamison D. ...
ISCA
2009
IEEE
318views Hardware» more  ISCA 2009»
14 years 3 months ago
Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boi...
Abhishek Bhattacharjee, Margaret Martonosi
QEST
2007
IEEE
14 years 3 months ago
A Petri Net Model for Evaluating Packet Buffering Strategies in a Network Processor
Previous studies have shown that buffering packets in DRAM is a performance bottleneck. In order to understand the impediments in accessing the DRAM, we developed a detailed Petri...
Girish B. C., R. Govindarajan
DATE
2004
IEEE
130views Hardware» more  DATE 2004»
14 years 12 days ago
Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology
This paper presents an environment based on SystemC for architecture specification of programmable systems. Making use of the new architecture description language ArchC, able to ...
Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Aze...
HASKELL
2006
ACM
14 years 2 months ago
Statically typed linear algebra in Haskell
Many numerical algorithms are specified in terms of operations on vectors and matrices. Matrix operations can be executed extremely efficiently using specialized linear algebra k...
Frederik Eaton