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ICCD
2001
IEEE
110views Hardware» more  ICCD 2001»
14 years 4 months ago
Low-Energy DSP Code Generation Using a Genetic Algorithm
This paper deals with low-energy code generation for a highly optimized digital signal processor designed for mobile communication applications. We present a genetic algorithm bas...
Markus Lorenz, Rainer Leupers, Peter Marwedel, Tho...
MICRO
2010
IEEE
149views Hardware» more  MICRO 2010»
13 years 5 months ago
ReMAP: A Reconfigurable Heterogeneous Multicore Architecture
This paper presents ReMAP, a reconfigurable architecture geared towards accelerating and parallelizing applications within a heterogeneous CMP. In ReMAP, threads share a common rec...
Matthew A. Watkins, David H. Albonesi
TC
2002
13 years 7 months ago
Architectures and VLSI Implementations of the AES-Proposal Rijndael
Two architectures and VLSI implementations of the AES Proposal, Rijndael, are presented in this paper. These alternative architectures are operated both for encryption and decrypti...
Nicolas Sklavos, Odysseas G. Koufopavlou
PPOPP
2006
ACM
14 years 1 months ago
Optimizing irregular shared-memory applications for distributed-memory systems
In prior work, we have proposed techniques to extend the ease of shared-memory parallel programming to distributed-memory platforms by automatic translation of OpenMP programs to ...
Ayon Basumallik, Rudolf Eigenmann
ASPDAC
2006
ACM
158views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Analysis of scratch-pad and data-cache performance using statistical methods
— An effectively designed and efficiently used memory hierarchy, composed of scratch-pads or cache, is seen today as the key to obtaining energy and performance gains in data-do...
Javed Absar, Francky Catthoor