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PDP
2009
IEEE
14 years 2 months ago
Phoenix: A Runtime Environment for High Performance Computing on Chip Multiprocessors
Abstract—Execution of applications on upcoming highperformance computing (HPC) systems introduces a variety of new challenges and amplifies many existing ones. These systems will...
Avneesh Pant, Hassan Jafri, Volodymyr V. Kindraten...
EUROPAR
2010
Springer
13 years 7 months ago
Power-Efficient Spilling Techniques for Chip Multiprocessors
Abstract. Current trends in CMPs indicate that the core count will increase in the near future. One of the main performance limiters of these forthcoming microarchitectures is the ...
Enric Herrero, José González, Ramon ...
DATE
2006
IEEE
114views Hardware» more  DATE 2006»
13 years 11 months ago
Compositional, efficient caches for a chip multi-processor
In current multi-media systems major parts of the functionality consist of software tasks executed on a set of concurrently operating processors. Those tasks interfere with each o...
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin ...
IEEEPACT
2009
IEEE
13 years 5 months ago
Core-Selectability in Chip Multiprocessors
Abstract--The centralized structures necessary for the extraction of instruction-level parallelism (ILP) are consuming progressively smaller portions of the total die area of chip ...
Hashem Hashemi Najaf-abadi, Niket Kumar Choudhary,...
ASPDAC
2008
ACM
154views Hardware» more  ASPDAC 2008»
13 years 9 months ago
Automated techniques for energy efficient scheduling on homogeneous and heterogeneous chip multi-processor architectures
Abstract-- We address performance maximization of independent task sets under energy constraint on chip multi-processor (CMP) architectures that support multiple voltage/frequency ...
Sushu Zhang, Karam S. Chatha