121 search results - page 3 / 25 » Performance evaluation for system-on-chip architectures usin... |
DATE
2003
IEEE
14 years 25 days ago
2003
IEEE
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...
DAC
2004
ACM
14 years 29 days ago
2004
ACM
System-on-Chip (SoC) designs are increasingly becoming more complex. Efficient on-chip communication architectures are critical for achieving desired performance in these systems....
MASCOTS
2000
13 years 9 months ago
2000
Most network engineering tools are unsatisfactory. Measurements are not predictive, simulations do not scale, and analysis is limited to oversimplified models. To be more useful, ...
PARLE
1992
13 years 11 months ago
1992
Complex and data-intensive database queries mandate parallel processing strategies to achieve sufficiently short response times. In praxis, parallel database processing is mostly b...
DATE
2005
IEEE
13 years 9 months ago
2005
IEEE
Transaction Level Modeling (TLM) approach is used to meet the simulation speed as well as cycle accuracy for large scale SoC performance analysis. We implemented a transaction-lev...