Sciweavers

290 search results - page 27 / 58
» Performance of Hardware Compressed Main Memory
Sort
View
DATE
2009
IEEE
135views Hardware» more  DATE 2009»
14 years 2 months ago
Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration
Reconfigurable Architectures are good candidates for application accelerators that cannot be set in stone at production time. FPGAs however, often suffer from the area and perfor...
Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi
VEE
2009
ACM
171views Virtualization» more  VEE 2009»
14 years 2 months ago
Dynamic memory balancing for virtual machines
Virtualization essentially enables multiple operating systems and applications to run on one physical computer by multiplexing hardware resources. A key motivation for applying vi...
Weiming Zhao, Zhenlin Wang
MICRO
2008
IEEE
139views Hardware» more  MICRO 2008»
14 years 2 months ago
Adaptive data compression for high-performance low-power on-chip networks
With the recent design shift towards increasing the number of processing elements in a chip, high-bandwidth support in on-chip interconnect is essential for low-latency communicat...
Yuho Jin, Ki Hwan Yum, Eun Jung Kim
IPPS
2003
IEEE
14 years 1 months ago
Reconfigurable Architecture Requirements for Co-Designed Virtual Machines
This paper addresses the physical hardware requirements necessary for a co-design hardware/software virtual machine to not only exist, but to also provide comparable performance w...
Kenneth B. Kent, Micaela Serra
DATE
2008
IEEE
107views Hardware» more  DATE 2008»
14 years 2 months ago
Merged Computation for Whirlpool Hashing
This paper presents an improved hardware structure for the computation of the Whirlpool hash function. By merging the round key computation with the data compression and by using ...
Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Sta...