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» Performance of Hardware Compressed Main Memory
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DATE
2003
IEEE
134views Hardware» more  DATE 2003»
14 years 1 months ago
A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration
The design of high performance multimedia systems in a short time force us to use IP's blocks in many designs. However, their correct integration in a design implies more com...
Adel Baganne, Imed Bennour, Mehrez Elmarzougui, Ri...
ASAP
2005
IEEE
104views Hardware» more  ASAP 2005»
14 years 1 months ago
Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application
Users expect future handhelddevices to provide extended multimedia functionality and have long battery life. This type of application imposes heavy constraints on performance and ...
Andy Lambrechts, Praveen Raghavan, Anthony Leroy, ...
HICSS
1997
IEEE
120views Biometrics» more  HICSS 1997»
14 years 10 days ago
Building the 4 Processor SB-PRAM Prototype
The SB-PRAM is a massively parallel, uniform memory access (UMA) shared memory computer. The main ideas of the design are multithreading on instruction level, hashing of the addre...
Peter Bach, Michael Braun, Arno Formella, Jör...
FCCM
2008
IEEE
114views VLSI» more  FCCM 2008»
14 years 2 months ago
Scaling Soft Processor Systems
As FPGA-based systems including soft-processors become increasingly common we are motivated to better understand the best way to scale the performance of such systems. In this pap...
Martin Labrecque, Peter Yiannacouras, J. Gregory S...
ICPR
2000
IEEE
14 years 16 days ago
Transparent Parallel Image Processing by way of a Familiar Sequential API
This paper describes an infrastructure that enables transparent development of image processing software for parallel computers. The infrastructure’s main component is an image ...
Frank J. Seinstra, Dennis Koelma