69 search results - page 11 / 14 » Performance of Switch Blocking on Multithreaded Architecture... |
ICITA
2005
IEEE
14 years 2 months ago
2005
IEEE
In this paper, we investigate the dynamic RWA problem in networks comprising of all-optical switches based on the multi-granular architecture (MG_DRWA). With this adaptive archite...
ISCAS
2006
IEEE
14 years 2 months ago
2006
IEEE
— Low-density parity-check convolutional codes offer the same good error-correcting performance as low-density parity-check block codes while having the ability to encode and dec...
IPPS
1999
IEEE
14 years 26 days ago
1999
IEEE
The rapid progress in high-performance microprocessor design has made it di cult to adapt real-time scheduling results to new models of microprocessor hardware, thus leaving an un...
IEEEPACT
2007
IEEE
14 years 2 months ago
2007
IEEE
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...
DAC
1997
ACM
14 years 23 days ago
1997
ACM
This paper describes a new design methodology to analyze the on-chip power supply noise for high performance microprocessors. Based on an integrated package-level and chip-level p...