69 search results - page 13 / 14 » Performance of Switch Blocking on Multithreaded Architecture... |
FPL
2007
Springer
14 years 2 months ago
2007
Springer
We are developing a set of reusable design blocks and several prototype systems for emulation of multi-core architectures in FPGAs. RAMP Blue is the first of these prototypes and...
DSD
2009
IEEE
14 years 3 months ago
2009
IEEE
—The scalability and performance of the Internet depends critically on the performance of its packet switches. Current packet switches are based on single-hop crossbar fabrics, w...
SLIP
2005
ACM
14 years 2 months ago
2005
ACM
The interconnection architecture of FPGAs such as switches dominates performance of FPGAs. Three-dimensional integration of FPGAs overcomes interconnect limitations by allowing in...
IEEEPACT
2005
IEEE
14 years 2 months ago
2005
IEEE
Current integration trends embrace the prosperity of single-chip multi-core processors. Although multi-core processors deliver significantly improved system throughput, single-thr...
SASP
2009
IEEE
14 years 3 months ago
2009
IEEE
—This paper describes a multi-threaded parallel design and implementation of the Smith-Waterman (SM) algorithm on compute unified device architecture (CUDA)-compatible graphic pr...