955 search results - page 10 / 191 » Performance optimization of multiple memory architectures fo... |
128
Voted
ISSS
1997
IEEE
15 years 6 months ago
1997
IEEE
Embedded processor-based systems allow for the tailoring of the on-chip memory architecture based on application-specific requirements. We present an analytical strategy for explo...
134
Voted
PCI
2005
Springer
15 years 8 months ago
2005
Springer
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...
114
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MICRO
2002
IEEE
15 years 7 months ago
2002
IEEE
Instruction cache aware compilation seeks to lay out a program in memory in such a way that cache conflicts between procedures are minimized. It does this through profile-driven...
117
Voted
NPC
2005
Springer
15 years 8 months ago
2005
Springer
This paper focuses on the Cyclops64 computer architecture and presents an analytical model and performance simulation results for the preloading and loop unrolling approaches to op...
128
Voted
MASCOTS
2008
15 years 4 months ago
2008
Galois field implementations are central to the design of many reliable and secure systems, with many systems implementing them in software. The two most common Galois field opera...