955 search results - page 36 / 191 » Performance optimization of multiple memory architectures fo... |
IPPS
2010
IEEE
13 years 7 months ago
2010
IEEE
The memory hierarchy of most multicore systems contains one or more levels of cache that is shared among multiple cores. The shared-cache architecture presents many opportunities f...
ICPP
1998
IEEE
14 years 1 months ago
1998
IEEE
Many large scale applications, have significant I/O requirements as well as computational and memory requirements. Unfortunately, limited number of I/O nodes provided by the conte...
DATE
1998
IEEE
14 years 1 months ago
1998
IEEE
As the "system-on-a-chip" concept is rapidly becoming a reality, time-to-market and product complexity push the reuse of complex macromodules. Circuits combining a varie...
EUROPAR
2009
Springer
14 years 3 months ago
2009
Springer
Moore’s Law suggests that the number of processing cores on a single chip increases exponentially. The future performance increases will be mainly extracted from thread-level par...
CASES
2003
ACM
14 years 2 months ago
2003
ACM
Code size has always been an important issue for all embedded applications as well as larger systems. Code compression techniques have been devised as a way of battling bloated co...