955 search results - page 48 / 191 » Performance optimization of multiple memory architectures fo... |
CCGRID
2001
IEEE
14 years 22 days ago
2001
IEEE
Active networks allow computations to be performed innetwork at routers as messages pass through them. Active networks offer unique opportunities to optimize networkcentric applic...
ISQED
2002
IEEE
14 years 2 months ago
2002
IEEE
This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemente...
ISCA
2010
IEEE
14 years 2 months ago
2010
IEEE
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
ICNS
2007
IEEE
14 years 3 months ago
2007
IEEE
To build holistic protection against complex and blended network threats, multiple security features need to be integrated into a unified security architecture, which requires in ...
ARC
2010
Springer
14 years 3 months ago
2010
Springer
In this paper, we present the Quantitative Usage Analysis of Data (QUAD) tool, a sophisticated memory access tracing tool that provides a comprehensive quantitative analysis of mem...