58 search results - page 5 / 12 » Performance-oriented placement and routing for field-program... |
DATE
2009
IEEE
14 years 1 months ago
2009
IEEE
In this paper, we propose a preprocessing method to improve Side Channel Attacks (SCAs) on Dual-rail with Precharge Logic (DPL) countermeasure family. The strength of our method i...
ICCAD
2003
IEEE
14 years 3 months ago
2003
IEEE
As Field-Programmable Gate Array (FPGA) power consumption continues to increase, lower power FPGA circuitry, architectures, and Computer-Aided Design (CAD) tools need to be develo...
FPL
2003
Springer
14 years 7 days ago
2003
Springer
This paper describes a lightweight Field Programmable Gate Array (FPGA) circuit design that supports the simultaneous programming of multiple devices at different locations throug...
EURODAC
1995
IEEE
13 years 10 months ago
1995
IEEE
This paper presents a performance-oriented placement and routing tool for field-programmable gate arrays. Using recursive geometric partitioning for simultaneous placement and glo...
CEC
2005
IEEE
14 years 20 days ago
2005
IEEE
A genetic algorithm approach for segmented channel routing in field programmable gate arrays (FPGA's) is presented in this paper. The FPGA segmented channel routing problem (F...