43 search results - page 4 / 9 » Physical Synthesis for CPLD Architectures |
FPGA
2004
ACM
14 years 1 months ago
2004
ACM
The cost functions used to evaluate logic synthesis transformations for FPGAs are far removed from the final speed and routability determined after placement, routing and timing a...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents the Block Processing Engine (BPE), an Application Specific Instruction-Set Processor (ASIP) explicitly designed for the implementation of multistandard wireles...
GLVLSI
2009
IEEE
14 years 2 months ago
2009
IEEE
In the context of nanoscale networks-on-chip (NoCs), each link implementation solution is not just a specific synthesis optimization technique with local performance and power im...
DAC
2004
ACM
14 years 1 months ago
2004
ACM
A Module-Rased design flow for digital ICs with hard and sofl modules is presented. Versions of the sofl modules are implemented with different areddelay characteristics. The vers...
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
Thermal effects are becoming increasingly important during integrated circuit design. Thermal characteristics influence reliability, power consumption, cooling costs, and performan...