301 search results - page 23 / 61 » Physical design techniques for optimizing RTA-induced variat... |
VLSID
2005
IEEE
14 years 8 months ago
2005
IEEE
: The direct result of shrinking devices is not only higher densities but also increased switching activity and thus higher device temperatures. The variation in temperature over t...
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
NBTI (Negative Bias Temperature Instability) has emerged as the dominant PMOS device failure mechanism for sub100nm VLSI designs. There is little research to quantify its impact o...
DAC
2004
ACM
14 years 9 months ago
2004
ACM
Logic duplication, a commonly used synthesis technique to remove trapped inverters in reconvergent paths of Domino circuits, incurs high area and power penalties. In this paper, w...
PODS
2002
ACM
14 years 8 months ago
2002
ACM
We consider the fundamental operation of applying a conjunction of selection conditions to a set of records. With large main memories available cheaply, systems may choose to keep...
ICCAD
1991
IEEE
13 years 12 months ago
1991
IEEE
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...