301 search results - page 8 / 61 » Physical design techniques for optimizing RTA-induced variat... |
FPGA
2007
ACM
14 years 2 months ago
2007
ACM
Chip design in the nanometer regime is becoming increasingly difficult due to process variations. ASIC designers have adopted statistical optimization techniques to mitigate the e...
GMP
2006
IEEE
14 years 2 months ago
2006
IEEE
Physical based and geometric based variational techniques for surface construction have been shown to be advanced methods for designing high quality surfaces in the fields of CAD ...
DAC
1999
ACM
14 years 9 months ago
1999
ACM
We propose a method for power optimization that considers glitch reduction by gate sizing based on the statistical estimation of glitch transitions. Our method reduces not only th...
DAC
1996
ACM
14 years 17 days ago
1996
ACM
1- A methodology is presented in this paper for determining an optimal set of clock path delays for designing high performance VLSI/ULSI-based clock distribution networks. This met...
PIMRC
2010
IEEE
13 years 6 months ago
2010
IEEE
Abstract--This paper addresses the fairness of Medium Access Control (MAC) protocols that are capable of handling interference on the physical layer to a varying extent. The variat...