Chip design in the nanometer regime is becoming increasingly difficult due to process variations. ASIC designers have adopted statistical optimization techniques to mitigate the e...
Physical based and geometric based variational techniques for surface construction have been shown to be advanced methods for designing high quality surfaces in the fields of CAD ...
We propose a method for power optimization that considers glitch reduction by gate sizing based on the statistical estimation of glitch transitions. Our method reduces not only th...
1- A methodology is presented in this paper for determining an optimal set of clock path delays for designing high performance VLSI/ULSI-based clock distribution networks. This met...
Abstract--This paper addresses the fairness of Medium Access Control (MAC) protocols that are capable of handling interference on the physical layer to a varying extent. The variat...
Ulrike Korger, Yingrui Chen, Christian Hartmann, K...