3 search results - page 1 / 1 » Physical-aware simulated annealing optimization of gate leak... |
DATE
2006
IEEE
14 years 26 days ago
2006
IEEE
For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorith...
TIM
2010
13 years 1 months ago
2010
In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the ...
MICRO
2003
IEEE
14 years 2 days ago
2003
IEEE
High-performance caches statically pull up the bitlines in all cache subarrays to optimize cache access latency. Unfortunately, such an architecture results in a significant wast...