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» Pipeline Vectorization for Reconfigurable Systems
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DATE
2009
IEEE
149views Hardware» more  DATE 2009»
14 years 2 months ago
An ILP formulation for task mapping and scheduling on multi-core architectures
Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. Key issues of designing such systems are on-chip interconnects, memory a...
Ying Yi, Wei Han, Xin Zhao, Ahmet T. Erdogan, Tugh...
TC
2011
13 years 2 months ago
StageNet: A Reconfigurable Fabric for Constructing Dependable CMPs
—CMOS scaling has long been a source of dramatic performance gains. However, semiconductor feature size reduction has resulted in increasing levels of operating temperatures and ...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott ...
ISCA
2000
IEEE
156views Hardware» more  ISCA 2000»
14 years 2 days ago
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Reconfigurable hardware has the potential for significant performance improvements by providing support for application−specific operations. We report our experience with Chimae...
Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithv...
ERSA
2006
113views Hardware» more  ERSA 2006»
13 years 9 months ago
Efficient FPGA-based Implementations of the MIMO-OFDM Physical Layer
- In this paper, we present a prototype FPGA design for an efficient physical layer implementation of a MIMO-OFDM technique. We propose a pipelined architecture using a Fast Fourie...
Jeoong Sung Park, Hong-Jip Jung, Viktor K. Prasann...
ESI
2010
97views more  ESI 2010»
13 years 6 months ago
A flexible streaming software architecture for scientific instruments
The recently completed prototyping efforts for a new type of riometer, the Advanced Rio-Imaging Experiment in Scandinavia (ARIES), required the development of a uniquely flexible s...
Martin Grill, Keith Barratt, Farideh Honary