192 search results - page 23 / 39 » Pipelined FPGA Adders |
RSP
2008
IEEE
14 years 2 months ago
2008
IEEE
ASIP-based implementations constitute a key trend in SoC design enabling optimal tradeoffs between performance and flexibility. This paper details a case study of an ASIP-based im...
GLVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. U...
FPL
2010
Springer
13 years 6 months ago
2010
Springer
Heterogeneous or co-processor architectures are becoming an important component of high productivity computing systems (HPCS). In this work the performance of a GPU based HPCS is c...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computatio...
CHES
2007
Springer
14 years 2 months ago
2007
Springer
The hardness of the integer factorization problem assures the security of some public-key cryptosystems including RSA, and the number field sieve method (NFS), the most efficient ...