351 search results - page 56 / 71 » Plug-and-Play Architectural Design and Verification |
DATE
1999
IEEE
13 years 11 months ago
1999
IEEE
This paper describes a simulation technique for RealTime Hw/Sw systems based on an object executable model. It allows designers to seamlessly estimate and verify their solutions f...
DAC
2002
ACM
14 years 7 months ago
2002
ACM
We propose Satisfiability Checking (SAT) techniques that lead to a consistent performance improvement of up to 3x over state-ofthe-art SAT solvers like Chaff on important problem ...
DAC
2004
ACM
14 years 7 months ago
2004
ACM
The increasing complexity of today's mixed-signal integrated circuits necessitates both top-down and bottom-up system-level verification. Time-domain state-space modeling and...
SIGSOFT
2007
ACM
14 years 7 months ago
2007
ACM
When enacting a web service orchestration defined using the Business Process Execution Language (BPEL) we observed various safety property violations. This surprised us considerab...
HPCA
2008
IEEE
14 years 7 months ago
2008
IEEE
The continued scaling of device dimensions and the operating voltage reduces the critical charge and thus natural noise tolerance level of transistors. As a result, circuits can p...