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FPL
2000
Springer
119views Hardware» more  FPL 2000»
13 years 11 months ago
A Self-Reconfigurable Gate Array Architecture
Abstract. This paper presents an innovative architecture for a reconfigurable device that allows single cycle context switching and single cycle random access to the unified on-chi...
Reetinder P. S. Sidhu, Sameer Wadhwa, Alessandro M...
DATE
2006
IEEE
88views Hardware» more  DATE 2006»
14 years 1 months ago
Temporal partitioning for image processing based on time-space complexity in reconfigurable architectures
Temporal partitioning techniques are useful to implement large and complex applications, which can be split into partitions in FPGA devices. In order to minimize resources, each o...
Paulo Sérgio B. do Nascimento, Manoel Euseb...
FPGA
2009
ACM
285views FPGA» more  FPGA 2009»
14 years 2 months ago
PERG-Rx: a hardware pattern-matching engine supporting limited regular expressions
PERG is a pattern matching engine designed for locating predefined byte string patterns (rules) from the ClamAV virus signature database in a data stream. This paper presents PERG...
Johnny Tsung Lin Ho, Guy G. Lemieux
ERSA
2007
194views Hardware» more  ERSA 2007»
13 years 8 months ago
A Scalable and Reconfigurable Shared-Memory Graphics Cluster Architecture
Abstract: If the computational demands of an interactive graphics rendering application cannot be met by a single commodity Graphics Processing Unit (GPU), multiple graphics accele...
Ross Brennan, Michael Manzke, Keith O'Conor, John ...
FPL
2003
Springer
146views Hardware» more  FPL 2003»
14 years 19 days ago
Domain-Specific Reconfigurable Array for Distributed Arithmetic
Distributed Arithmetic techniques are widely used to implement Sum-of-Products computations such as calculations found in multimedia applications like FIR filtering and Discrete Co...
Sami Khawam, Tughrul Arslan, Fred Westall