51 search results - page 10 / 11 » Post-Layout Optimization for Deep Submicron Design |
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
With shrinking feature size and growing integration density in the Deep Sub-Micron technologies, the global buses are fast becoming the “weakest-links” in VLSI design. They ha...
DAC
2009
ACM
14 years 8 months ago
2009
ACM
Embedded cryptosystems show increased vulnerabilities to implementation attacks such as power analysis. CMOS technology trends are causing increased process variations which impac...
ISQED
2007
IEEE
14 years 1 months ago
2007
IEEE
In this paper, we address the interconnect-driven floorplanning problem that integrates OPC-friendly bus assignment with floorplanning. Buses consist of a number of horizontal/v...
ISPD
2004
ACM
14 years 1 months ago
2004
ACM
As the CMOS technology is scaled into the dimension of nanometer, the clock frequencies and die sizes of ICs are shown to be increasing steadily [5]. Today, global wires that requ...
ISCA
2008
IEEE
13 years 7 months ago
2008
IEEE
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...