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» Postsilicon Validation Methodology for Microprocessors
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MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
13 years 5 months ago
AVF Stressmark: Towards an Automated Methodology for Bounding the Worst-Case Vulnerability to Soft Errors
Soft error reliability is increasingly becoming a first-order design concern for microprocessors, as a result of higher transistor counts, shrinking device geometries and lowering ...
Arun A. Nair, Lizy Kurian John, Lieven Eeckhout
DATE
2005
IEEE
115views Hardware» more  DATE 2005»
14 years 1 months ago
Functional Coverage Driven Test Generation for Validation of Pipelined Processors
Functional verification of microprocessors is one of the most complex and expensive tasks in the current system-on-chip design process. A significant bottleneck in the validatio...
Prabhat Mishra, Nikil D. Dutt
TCAD
2008
167views more  TCAD 2008»
13 years 7 months ago
System-Level Dynamic Thermal Management for High-Performance Microprocessors
Abstract--Thermal issues are fast becoming major design constraints in high-performance systems. Temperature variations adversely affect system reliability and prompt worst-case de...
Amit Kumar 0002, Li Shang, Li-Shiuan Peh, Niraj K....
TCAD
2008
172views more  TCAD 2008»
13 years 7 months ago
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodr...
ISPASS
2006
IEEE
14 years 1 months ago
Automatic testcase synthesis and performance model validation for high performance PowerPC processors
The latest high-performance IBM PowerPC microprocessor, the POWER5 chip, poses challenges for performance model validation. The current stateof-the-art is to use simple hand-coded...
Robert H. Bell Jr., Rajiv R. Bhatia, Lizy K. John,...