1419 search results - page 13 / 284 » Power Droop Testing |
VTS
2002
IEEE
14 years 2 months ago
2002
IEEE
A device testing method called Transient Signal Analysis (TSA) is subjected to elements of a real process and testing environment in this paper. Simulations experiments are design...
ITC
2003
IEEE
14 years 3 months ago
2003
IEEE
Scan-based architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we present a new technique that allows to design power-optimized...
DAC
2007
ACM
14 years 10 months ago
2007
ACM
Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can...
ICCD
2006
IEEE
14 years 6 months ago
2006
IEEE
— In this paper, we are proposing a core-based test methodology that utilizes the functional bus for test stimuli and response transportation. An efficient algorithm for the gen...
ASPDAC
2007
ACM
14 years 1 months ago
2007
ACM
As the large size of test data volume is becoming one of the major problems in testing System-on-a-Chip (SoC), several compression coding schemes have been proposed. Extended frequ...