1419 search results - page 24 / 284 » Power Droop Testing |
DAC
2005
ACM
13 years 11 months ago
2005
ACM
This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. By exploiting the use of multiple shift frequencies, the proposed meth...
DT
2006
13 years 10 months ago
2006
The ITRS (International Technology Roadmap for Semiconductors) predicts aggressive scaling down of device size, transistor threshold voltage and oxide thickness to meet growing de...
DATE
2002
IEEE
14 years 2 months ago
2002
IEEE
Optimizing power consumption at high-level is a critical step towards power-efficient digital system designs. This paper addresses the power management problem by scheduling a giv...
DATE
2009
IEEE
14 years 4 months ago
2009
IEEE
— In this paper, we present an X-Fill (QC-Fill) method for not only slashing the test time but also reducing the test power (including both capture power and shifting power). QC-...
ATS
2004
IEEE
14 years 1 months ago
2004
IEEE
Conventional serial connection of internal scan chains brings the power and time penalty. A novel parallel core wrapper design (pCWD) approach is presented in this paper for reduc...