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ASPDAC
2008
ACM
122views Hardware» more  ASPDAC 2008»
13 years 11 months ago
Total power optimization combining placement, sizing and multi-Vt through slack distribution management
Power dissipation is quickly becoming one of the most important limiters in nanometer IC design for leakage increases exponentially as the technology scaling down. However, power ...
Tao Luo, David Newmark, David Z. Pan
MTV
2006
IEEE
98views Hardware» more  MTV 2006»
14 years 4 months ago
Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study
Simulation-based validation of the current industrial processors typically use huge number of test programs generated at instruction set architecture (ISA) level. However, archite...
Heon-Mo Koo, Prabhat Mishra, Jayanta Bhadra, Magdy...
VTS
2005
IEEE
95views Hardware» more  VTS 2005»
14 years 3 months ago
SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms
Testing data retention faults (DRFs), particularly in integrated systems on chip comprised of very large number of various sizes and types of embedded SRAMs is challenging and typ...
Baosheng Wang, Yuejian Wu, Josh Yang, André...
ITC
1991
IEEE
80views Hardware» more  ITC 1991»
14 years 1 months ago
An Intelligent Approach to Automatic Test Equipment
In diagnosing a failed system, a smart technician would choose tests to be performed based on the context of the situation. Currently, test program sets do not fault-. isolate wit...
William R. Simpson, John W. Sheppard
SSIRI
2010
13 years 8 months ago
A Formal Framework for Mutation Testing
— Model-based approaches, especially based on directed graphs (DG), are becoming popular for mutation testing as they enable definition of simple, nevertheless powerful, mutation...
Fevzi Belli, Mutlu Beyazit