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HIPEAC
2010
Springer
15 years 8 months ago
Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions
Abstract. Customizable processors augmented with application-specific Instruction Set Extensions (ISEs) have begun to gain traction in recent years. The most effective ISEs include...
Theo Kluter, Samuel Burri, Philip Brisk, Edoardo C...
ISLPED
2010
ACM
165views Hardware» more  ISLPED 2010»
15 years 6 months ago
Dynamic workload characterization for power efficient scheduling on CMP systems
Runtime characteristics of individual threads (such as IPC, cache usage, etc.) are a critical factor in making efficient scheduling decisions in modern chip-multiprocessor systems...
Gaurav Dhiman, Vasileios Kontorinis, Dean M. Tulls...
DATE
2005
IEEE
143views Hardware» more  DATE 2005»
15 years 11 months ago
Q-DPM: An Efficient Model-Free Dynamic Power Management Technique
When applying Dynamic Power Management (DPM) technique to pervasively deployed embedded systems, the technique needs to be very efficient so that it is feasible to implement the t...
Min Li, Xiaobo Wu, Richard Yao, Xiaolang Yan
ASPLOS
2004
ACM
15 years 11 months ago
Continual flow pipelines
Increased integration in the form of multiple processor cores on a single die, relatively constant die sizes, shrinking power envelopes, and emerging applications create a new cha...
Srikanth T. Srinivasan, Ravi Rajwar, Haitham Akkar...
ISLPED
2003
ACM
115views Hardware» more  ISLPED 2003»
15 years 11 months ago
Reducing energy and delay using efficient victim caches
In this paper, we investigate methods for improving the hit rates in the first level of memory hierarchy. Particularly, we propose victim cache structures to reduce the number of ...
Gokhan Memik, Glenn Reinman, William H. Mangione-S...