1238 search results - page 113 / 248 » Power Efficient Processor Architecture and The Cell Processo... |
154
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CHES
2010
Springer
15 years 7 months ago
2010
Springer
In this paper, a thorough bottom-up optimization process (field, point and scalar arithmetic) is used to speed up the computation of elliptic curve point multiplication and report ...
146
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ICIP
2003
IEEE
16 years 7 months ago
2003
IEEE
The Integer Cosine Transform (ICT) has been shown to be an alternative to the DCT for image processing. This paper presents a parallel-pipelined architecture of an 8x8 ICT(10, 9, ...
149
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DATE
2006
IEEE
16 years 7 days ago
2006
IEEE
This paper presents the Block Processing Engine (BPE), an Application Specific Instruction-Set Processor (ASIP) explicitly designed for the implementation of multistandard wireles...
166
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SIGOPSE
1998
ACM
15 years 10 months ago
1998
ACM
MMLite is a modular system architecture that is suitable for a wide variety of hardware and applications. The system provides a selection of object-based components that are dynam...
195
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DAC
2006
ACM
16 years 7 months ago
2006
ACM
Most existing dynamic voltage scaling (DVS) schemes for multiple tasks assume an energy cost function (energy consumption versus execution time) that is independent of the task ch...