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ICCD
2003
IEEE
123views Hardware» more  ICCD 2003»
16 years 3 months ago
Simplifying SoC design with the Customizable Control Processor Platform
With the circuit density available in today’s ASIC design systems, increased integration is possible creating more complexity in the design of a System on a Chip (SoC). IBM’s ...
C. Ross Ogilvie, Richard Ray, Robert Devins, Mark ...
DATE
2003
IEEE
109views Hardware» more  DATE 2003»
15 years 11 months ago
A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors
This paper presents a new algorithm for on-the-fly data compression in high performance VLIW processors. The algorithm aggressively targets energy minimization of some of the domi...
Alberto Macii, Enrico Macii, Fabrizio Crudo, Rober...
ITC
2003
IEEE
138views Hardware» more  ITC 2003»
15 years 11 months ago
Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint
Scan-based architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we present a new technique that allows to design power-optimized...
Yannick Bonhomme, Patrick Girard, Loïs Guille...
FPGA
2004
ACM
119views FPGA» more  FPGA 2004»
15 years 11 months ago
A quantitative analysis of the speedup factors of FPGAs over processors
The speedup over a microprocessor that can be achieved by implementing some programs on an FPGA has been extensively reported. This paper presents an analysis, both quantitative a...
Zhi Guo, Walid A. Najjar, Frank Vahid, Kees A. Vis...
PROCEDIA
2010
148views more  PROCEDIA 2010»
15 years 26 days ago
SysCellC: a data-flow programming model on multi-GPU
High performance computing with low cost machines becomes a reality with GPU. Unfortunately, high performances are achieved when the programmer exploits the architectural specific...
Dominique Houzet, Sylvain Huet, Anis Rahman