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» Power Estimation in Sequential Circuits
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ISLPED
1995
ACM
96views Hardware» more  ISLPED 1995»
13 years 11 months ago
Towards a high-level power estimation capability
We will present a power estimation technique for digital integrated circuits that operates at the register transfer level RTL. Such a high-level power estimation capability is r...
Farid N. Najm
DAC
1997
ACM
14 years 7 days ago
Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT
We describe an architectural design space exploration methodology that minimizes the energy dissipation of digital circuits. The centerpiece of our methodology is a Verilog-based ...
Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha C...
BMCBI
2011
13 years 2 months ago
Sequential Interim Analyses of Survival Data in DNA Microarray Experiments
Background: Discovery of biomarkers that are correlated with therapy response and thus with survival is an important goal of medical research on severe diseases, e.g. cancer. Freq...
Andreas Leha, Tim Beißbarth, Klaus Jung
ISPD
1998
ACM
91views Hardware» more  ISPD 1998»
14 years 8 days ago
Estimation of maximum current envelope for power bus analysis and design
In this paper we present an input pattern independent method to compute the maximum current envelope, which is an upper bound over all possible current waveforms drawn by a circui...
Sudhakar Bobba, Ibrahim N. Hajj
FPL
2005
Springer
115views Hardware» more  FPL 2005»
14 years 1 months ago
Statistical Power Estimation for FPGA
This article presents a power estimation tool integrated with an FPGA design flow. It is able to estimate total and individual-node average power consumption for combinational blo...
Elias Todorovich, Fabian Angarita, Javier Valls, E...