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» Power Estimation in Sequential Circuits
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ICCAD
2007
IEEE
164views Hardware» more  ICCAD 2007»
14 years 4 months ago
Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques
— The need to perform power analysis in the early stages of the design process has become critical as power has become a major design constraint. Embedded and highperformance mic...
Xiaoyao Liang, Kerem Turgay, David Brooks
ISLPED
2003
ACM
83views Hardware» more  ISLPED 2003»
14 years 1 months ago
Leakage power modeling and optimization in interconnection networks
Power will be the key limiter to system scalability as interconnection networks take up an increasingly significant portion of system power. In this paper, we propose an architec...
Xuning Chen, Li-Shiuan Peh
ICCAD
2010
IEEE
125views Hardware» more  ICCAD 2010»
13 years 6 months ago
Peak current reduction by simultaneous state replication and re-encoding
Reducing circuit's peak current plays an important role in circuit reliability in deep sub-micron era. For sequential circuits, it is observed that the peak current has a str...
Junjun Gu, Gang Qu, Lin Yuan, Qiang Zhou
ASPDAC
2005
ACM
92views Hardware» more  ASPDAC 2005»
13 years 10 months ago
Sleep transistor sizing using timing criticality and temporal currents
— Power gating is a circuit technique that enables high performance and low power operation. One of the challenges in power gating is sizing the sleep transistor which is used to...
Anand Ramalingam, Bin Zhang, Anirudh Devgan, David...
DAC
2004
ACM
14 years 9 months ago
An analytical approach for dynamic range estimation
It has been widely recognized that the dynamic range information of an application can be exploited to reduce the datapath bitwidth of either processors or ASICs, and therefore th...
Bin Wu, Jianwen Zhu, Farid N. Najm