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» Power Macromodeling for High Level Power Estimation
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TVLSI
1998
109views more  TVLSI 1998»
13 years 7 months ago
Power estimation of embedded systems: a hardware/software codesign approach
— The need for low-power embedded systems has become very significant within the microelectronics scenario in the most recent years. A power-driven methodology is mandatory duri...
William Fornaciari, Paolo Gubian, Donatella Sciuto...
ICCAD
2001
IEEE
143views Hardware» more  ICCAD 2001»
14 years 4 months ago
Transient Power Management Through High Level Synthesis
The use of nanometer technologies is making it increasingly important to consider transient characteristics of a circuit’s power dissipation (e.g., peak power, and power gradien...
Vijay Raghunathan, Srivaths Ravi, Anand Raghunatha...
DSD
2006
IEEE
107views Hardware» more  DSD 2006»
14 years 1 months ago
A High Level Power Model for the Nostrum NoC
We propose a power model for the Nostrum NoC. For this purpose an empirical power model of links and switches has been formulated and validated with the Synopsys Power Compiler. T...
Sandro Penolazzi, Axel Jantsch
VLSID
2007
IEEE
104views VLSI» more  VLSID 2007»
14 years 1 months ago
STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs
In this paper we demonstrate the impact of the floorplan on the temperature-dependent leakage power of a System on Chip (SoC). We propose a novel system level temperature aware a...
Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal...
ASPLOS
2009
ACM
14 years 8 months ago
PowerNap: eliminating server idle power
Data center power consumption is growing to unprecedented levels: the EPA estimates U.S. data centers will con
David Meisner, Brian T. Gold, Thomas F. Wenisch