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» Power Macromodeling for High Level Power Estimation
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ITC
2002
IEEE
97views Hardware» more  ITC 2002»
14 years 17 days ago
RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST
Marcelino B. Santos, Isabel C. Teixeira, Joã...
ISSS
1996
IEEE
94views Hardware» more  ISSS 1996»
13 years 11 months ago
Synthesis of Low-Power Selectively-Clocked Systems from High-Level Specification
Luca Benini, Patrick Vuillod, Claudionor Jos&eacut...
JISE
2007
43views more  JISE 2007»
13 years 7 months ago
A Tableless Approach for High-Level Power Modeling Using Neural Networks
Chih-Yang Hsu, Wen-Tsan Hsieh, Chien-Nan Jimmy Liu...
DAC
2005
ACM
14 years 8 months ago
Power emulation: a new paradigm for power estimation
In this work, we propose a new paradigm called power emulation, which exploits hardware acceleration to drastically speedup power estimation. Power emulation is based on the obser...
Joel Coburn, Srivaths Ravi, Anand Raghunathan