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» Power Macromodeling for High Level Power Estimation
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VLSID
2002
IEEE
114views VLSI» more  VLSID 2002»
16 years 4 months ago
Embedded DRAM (eDRAM) Power-Energy Estimation for System-on-a-Chip (SoC) Applications
Embedded DRAM (eDRAM) power-energy estimation is presented for system-on-a-chip (SOC) applications. The main feature is the signal swing based analytic (SSBA) model, which improve...
Yong-Ha Park, Jeonghoon Kook, Hoi-Jun Yoo
BMCBI
2005
62views more  BMCBI 2005»
15 years 4 months ago
Differences in codon bias cannot explain differences in translational power among microbes
Background: Translational power is the cellular rate of protein synthesis normalized to the biomass invested in translational machinery. Published data suggest a previously unreco...
Les Dethlefsen, Thomas M. Schmidt
DAC
2004
ACM
16 years 5 months ago
Statistical optimization of leakage power considering process variations using dual-Vth and sizing
timing analysis tools to replace standard deterministic static timing analyzers whereas [8,27] develop approaches for the statistical estimation of leakage power considering within...
Ashish Srivastava, Dennis Sylvester, David Blaauw
VLSID
2008
IEEE
142views VLSI» more  VLSID 2008»
15 years 10 months ago
Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures
With the shift towards deep sub-micron (DSM) technologies, the increase in leakage power and the adoption of poweraware design methodologies have resulted in potentially significa...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
FDL
2003
IEEE
15 years 9 months ago
Design and Power Analysis in SysteC of an I2C Bus Driver
The paper presents a methodology to integrate information on power consumption in a high level functional description of a System-on-chip. The power dissipated during the executio...
Marco Caldari, Massimo Conti, Paolo Crippa, Simone...