979 search results - page 42 / 196 » Power Macromodeling for High Level Power Estimation |
ISVLSI
2002
IEEE
14 years 20 days ago
2002
IEEE
The clock distribution and generation circuitry is known to consume more than a quarter of the power budget of existing microprocessors. A previously derived clock energy model is...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
In this paper we address the the growing issue of junction tunneling leakage (Ijunc) at the circuit level. Specifically, we develop a fast approach to analyze the state-dependent ...
ICASSP
2011
IEEE
12 years 11 months ago
2011
IEEE
We consider the problem of minimizing the cost of the power required to achieve a specified level of quality-of-service (QoS) on a point-to-point link that may be assisted by an ...
ISLPED
1999
ACM
14 years 2 days ago
1999
ACM
Modern microprocessors employ one or two levels of on-chip cachesto bridge the burgeoning speeddisparities between the processor and the RAM. These SRAM caches are a major source ...
DAC
1999
ACM
14 years 2 days ago
1999
ACM
In deep submicron technology, IR-drop and clock skew issues become more crucial to the functionality of chip. This paper presents a oorplan-based power and clock distribution meth...