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» Power Optimization in Current Mode Circuits
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ISCAS
2005
IEEE
119views Hardware» more  ISCAS 2005»
14 years 1 months ago
Analysis of power consumption in VLSI global interconnects
Abstract— The analysis of effects induced by interconnects become increasingly important as the scale of process technologies steadily shrinks. While most analyses focus on the t...
Youngsoo Shin, Hyung-Ock Kim
ASPDAC
2001
ACM
75views Hardware» more  ASPDAC 2001»
13 years 11 months ago
Integrated power supply planning and floorplanning
One of the most challenging issues in today's high-performance VLSI design is to ensure high-quality power supply to each individual circuit blocks. Reduced power supply volt...
I-Min Liu, Hung-Ming Chen, Tan-Li Chou, Adnan Aziz...
DAC
2006
ACM
14 years 8 months ago
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing
Subthreshold circuit designs have been demonstrated to be a successful alternative when ultra-low power consumption is paramount. However, the characteristics of MOS transistors i...
John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S....
VLSID
2007
IEEE
120views VLSI» more  VLSID 2007»
14 years 8 months ago
Statistical Leakage and Timing Optimization for Submicron Process Variation
Leakage power is becoming a dominant contributor to the total power consumption and dual-Vth assignment is an efficient technique to decrease leakage power, for which effective de...
Yuanlin Lu, Vishwani D. Agrawal
ISLPED
2005
ACM
86views Hardware» more  ISLPED 2005»
14 years 1 months ago
An evaluation of code and data optimizations in the context of disk power reduction
Disk power management is becoming increasingly important in high-end server and cluster type of environments that execute dataintensive applications. While hardware-only approache...
Mahmut T. Kandemir, Seung Woo Son, Guangyu Chen