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» Power Optimization of Variable Voltage Core-Based Systems
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TIM
2010
294views Education» more  TIM 2010»
13 years 2 months ago
Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems
In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the ...
HeungJun Jeon, Yong-Bin Kim, Minsu Choi
ISCAS
2007
IEEE
123views Hardware» more  ISCAS 2007»
14 years 1 months ago
Low-Power Low-Voltage Hot-Spot Tolerant Clocking with Suppressed Skew
— A methodology based on supply voltage optimization for lowering the power consumption and temperature fluctuations induced skew of clock distribution networks is proposed in th...
Sherif A. Tawfik, Volkan Kursun
DAC
2000
ACM
14 years 8 months ago
Run-time voltage hopping for low-power real-time systems
This paper presents a novel run-time dynamic voltage scaling scheme for low-power real-time systems. It employs software feedback control of supply voltage, which is applicable to...
Seongsoo Lee, Takayasu Sakurai
VTS
2005
IEEE
102views Hardware» more  VTS 2005»
14 years 1 months ago
Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance
Nanometer circuits are highly susceptible to soft errors generated by alpha-particle or atmospheric neutron strikes to circuit nodes. The reasons for the high susceptibility are t...
Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhij...
PATMOS
2005
Springer
14 years 1 months ago
Power - Performance Optimization for Custom Digital Circuits
This paper presents a modular optimization framework for custom digital circuits in the power – performance space. The method uses a static timer and a nonlinear optimizer to max...
Radu Zlatanovici, Borivoje Nikolic