430 search results - page 14 / 86 » Power Optimized Combinational Logic Design |
VLSID
2005
IEEE
14 years 8 months ago
2005
IEEE
We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current comparators. First, we present ...
TVLSI
2010
13 years 2 months ago
2010
In this paper, we present a low-power architectural synthesis system (LOPASS) for field-programmable gate-array (FPGA) designs with interconnect power estimation and optimization. ...
FPGA
2003
ACM
14 years 28 days ago
2003
ACM
This paper presents a flexible FPGA architecture evaluation framework, named fpgaEVA-LP, for power efficiency analysis of LUT-based FPGA architectures. Our work has several contri...
ISPD
1999
ACM
14 years 23 hour ago
1999
ACM
This paper presents a methodology to analyze signal integrity such as power voltage drop and clock skew in early stages of design, more specifically, when RTL-design and early flo...
CCE
2010
13 years 5 months ago
2010
This paper presents an approach for combined mass and energy integration in process synthesis and illustrates it at the thermochemical production of crude synthetic natural gas (S...