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» Power Optimized Combinational Logic Design
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GLOBECOM
2006
IEEE
14 years 4 months ago
Performance Analysis and Optimal Signal Designs for Minimum Decoding Complexity ABBA Codes
— ABBA codes, a class of quasi-orthogonal space-time block codes (STBC) proposed by Tirkkonen et al., have been studied extensively for various applications. Yuen et al. have rec...
Dung Ngoc Dao, Chintha Tellambura
ICCAD
2005
IEEE
98views Hardware» more  ICCAD 2005»
14 years 7 months ago
Clustering for processing rate optimization
Clustering (or partitioning) is a crucial step between logic synthesis and physical design in the layout of a large scale design. A design verified at the logic synthesis level m...
Chuan Lin, Jia Wang, Hai Zhou
FPGA
2007
ACM
185views FPGA» more  FPGA 2007»
14 years 4 months ago
Power-aware FPGA logic synthesis using binary decision diagrams
Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. In this work we present a power...
Kevin Oo Tinmaung, David Howland, Russell Tessier
DSD
2004
IEEE
104views Hardware» more  DSD 2004»
14 years 1 months ago
A Static Low-Power, High-Performance 32-bit Carry Skip Adder
In this paper, we present a full-static carry-skip adder designed to achieve low power dissipation and high-performance operation. To reduce the adder's delay and power consu...
Kai Chirca, Michael J. Schulte, John Glossner, Hao...
DAC
2006
ACM
14 years 11 months ago
Optimal simultaneous mapping and clustering for FPGA delay optimization
Both technology mapping and circuit clustering have a large impact on FPGA designs in terms of circuit performance, area, and power dissipation. Existing FPGA design flows carry o...
Joey Y. Lin, Deming Chen, Jason Cong