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» Power Optimized Combinational Logic Design
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ICCAD
2000
IEEE
159views Hardware» more  ICCAD 2000»
14 years 2 months ago
ACTIF: A High-Level Power Estimation Tool for Analog Continuous-Time-Filters
A tool is presented that gives a high-level estimation of the power consumed by an analog continuous-time OTA-C filter when given only high-level input parameters such as dynamic ...
Erik Lauwers, Georges G. E. Gielen
DAC
2000
ACM
14 years 2 months ago
CYCLONE: automated design and layout of RF LC-oscillators
This paper presents an automated, layout-aware RF LCoscillator design tool, called CYCLONE that delivers an accurate and optimal LC-oscillator design, from specification to layout...
Carl De Ranter, B. De Muer, Geert Van der Plas, Pe...
DAC
2008
ACM
13 years 12 months ago
Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...
Min Ni, Seda Ogrenci Memik
VLSID
2002
IEEE
107views VLSI» more  VLSID 2002»
14 years 10 months ago
Estimation of Maximum Power-Up Current
Power gating is emerging as a viable solution to reduction of leakage current. However, power gated circuits are different from the conventional designs in the sense that a power-...
Fei Li, Lei He, Kewal K. Saluja
DATE
2000
IEEE
124views Hardware» more  DATE 2000»
14 years 2 months ago
On the Generation of Multiplexer Circuits for Pass Transistor Logic
Pass Transistor Logic has attracted more and more interest during last years, since it has proved to be an attractive alternative to static CMOS designs with respect to area, perf...
Christoph Scholl, Bernd Becker