430 search results - page 40 / 86 » Power Optimized Combinational Logic Design |
TVLSI
2008
13 years 10 months ago
2008
Applications in computer networks often require high throughput access to large data structures for lookup and classification. While advanced algorithms exist to speed these search...
GLVLSI
2007
IEEE
13 years 12 months ago
2007
IEEE
We present a vector selection methodology for estimating the peak power dissipation in a CMOS logic circuit. The ultimate goal is to combine the speed of RT-level simulation with ...
ASYNC
2002
IEEE
14 years 3 months ago
2002
IEEE
This paper presents a novel variation of wave pipelining that we call “surfing.” In previous wave pipelined designs, timing uncertainty grows monotonically as events propagat...
DAC
1999
ACM
14 years 2 months ago
1999
ACM
This paper describes a two-state methodology for register transfer level (RTL) logic simulation in which the use of the Xstate is completely eliminated inside ASIC designs. Exampl...
ICCAD
1996
IEEE
14 years 2 months ago
1996
IEEE
We describe an algorithm for the synthesis and optimization of interface circuits for embedded system components such as microprocessors, memory ASIC, and network subsystems with ...