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ICCD
1996
IEEE
104views Hardware» more  ICCD 1996»
13 years 12 months ago
Latch Redundancy Removal Without Global Reset
For circuits where there may be latches with no reset line, we show how to replace some of them with combinational logic. All previous work in sequential optimization by latch rem...
Shaz Qadeer, Robert K. Brayton, Vigyan Singhal
FCCM
2006
IEEE
162views VLSI» more  FCCM 2006»
14 years 1 months ago
Power Visualization, Analysis, and Optimization Tools for FPGAs
This paper introduces the Low-Power Intelligent Tool Environment (LITE), an object oriented tool set designed for power visualization, analysis, and optimization. These tools lever...
Matthew French, Li Wang, Michael J. Wirthlin
GLVLSI
2007
IEEE
141views VLSI» more  GLVLSI 2007»
14 years 2 months ago
Transition-activity aware design of reduction-stages for parallel multipliers
We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the pri...
Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Osc...
DATE
2005
IEEE
109views Hardware» more  DATE 2005»
14 years 1 months ago
Design Method for Constant Power Consumption of Differential Logic Circuits
Side channel attacks are a major security concern for smart cards and other embedded devices. They analyze the variations on the power consumption to find the secret key of the en...
Kris Tiri, Ingrid Verbauwhede
GLOBECOM
2008
IEEE
14 years 2 months ago
Cross-Layer Design of Optimal Adaptation Technique over Selection-Combining Diversity Nakagami-m Fading Channels
— Adaptive modulation and antenna diversity are two important enabling techniques for future wireless network to meet demand for high data rate transmission. We study a Markov de...
Ashok K. Karmokar, Vijay K. Bhargava