430 search results - page 55 / 86 » Power Optimized Combinational Logic Design |
FPGA
2006
ACM
14 years 1 months ago
2006
ACM
This paper presents experimental measurements of the differences between a 90nm CMOS FPGA and 90nm CMOS Standard Cell ASICs in terms of logic density, circuit speed and power cons...
DAC
2001
ACM
14 years 11 months ago
2001
ACM
Cost effective systems use specialization to optimize factors such as power consumption, processing throughput, flexibility or combinations thereof. Reconfigurable systems obtain ...
ICCAD
2001
IEEE
14 years 7 months ago
2001
IEEE
In this paper a layout-aware RF synthesis methodology is presented. The methodology combines the power of a differential evolution algorithm with cost function response modeling a...
ISLPED
2009
ACM
14 years 2 months ago
2009
ACM
We present experimental analysis to exploit the sequence dependence on energy saving in error tolerant image processing. Our analysis shows that the error distributions depend not...
ISCA
2011
IEEE
13 years 1 months ago
2011
IEEE
Conventional high-performance processors utilize register renaming and complex broadcast-based scheduling logic to steer instructions into a small number of heavily-pipelined exec...