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ALGORITHMICA
2006
77views more  ALGORITHMICA 2006»
13 years 9 months ago
Scalable Parallel Algorithms for FPT Problems
Algorithmic methods based on the theory of fixed-parameter tractability are combined with powerful computational platforms to launch systematic attacks on combinatorial problems o...
Faisal N. Abu-Khzam, Michael A. Langston, Pushkar ...
VLSID
2007
IEEE
206views VLSI» more  VLSID 2007»
14 years 9 months ago
MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
DATE
2010
IEEE
118views Hardware» more  DATE 2010»
13 years 7 months ago
Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network
Abstract—On-chip interconnection network is a crucial design component in high-performance System-on-Chips (SoCs). Many of previous works have focused on the automation of its to...
Minje Jun, Sungroh Yoon, Eui-Young Chung
GLVLSI
2005
IEEE
147views VLSI» more  GLVLSI 2005»
14 years 2 months ago
1-V 7-mW dual-band fast-locked frequency synthesizer
This paper presents a fully integrated 1-V, dual band, fastlocked frequency synthesizer for IEEE 802.11 a/b/g WLAN applications. It can synthesize frequencies in the range of 2.4 ...
Vikas Sharma, Chien-Liang Chen, Chung-Ping Chen
EGH
2010
Springer
13 years 7 months ago
Hardware implementation of micropolygon rasterization with motion and defocus blur
Current GPUs rasterize micropolygons (polygons approximately one pixel in size) inefficiently. Additionally, they do not natively support triangle rasterization with jittered samp...
J. S. Brunhaver, Kayvon Fatahalian, Pat Hanrahan