430 search results - page 8 / 86 » Power Optimized Combinational Logic Design |
SPIN
2010
Springer
13 years 6 months ago
2010
Springer
In the field of communication networks, protocol engineers usually employ several tools focused on specific kinds of analysis, such as performance or correctness. This paper pres...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
Achieving design closure is one of the biggest headaches for modern VLSI designers. This problem is exacerbated by high-level design automation tools that ignore increasingly impo...
APCCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
— A data driven approach to design and optimization of low power combinational multipliers is presented. This technique depends on signal gating to avoid un-necessary computation...
DATE
2010
IEEE
14 years 24 days ago
2010
IEEE
Ambipolar devices have been reported in many technologies, including carbon nanotube field effect transistors (CNTFETs). The ambipolarity can be in-field controlled with a secon...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...